Integrated circuits are operated in environments where radiation-induced logic errors may occur, such as in outer space. In such environments, the integrated circuit is required to maintain data integrity during a single event upset. A single event upset is a radiation-induced error in the logic state of a signal within the integrated circuit. The logic error may be the result of a collision between a high-energy proton or a heavy ion (cosmic ray) and the semiconductor material that forms the integrated circuit. Such a collision produces a quantity of electron-hole pairs in circuitry within the integrated circuit that is generating the signal, with the quantity of electron-hole pairs being capable of altering the logic state of the signal.
To prevent single event upsets from causing erroneous operation of the integrated circuit, circuitry within the integrated circuit must be designed to withstand such upsets. As a result, static logic circuitry is typically used in place of dynamic logic circuitry to protect against single event upsets. While static logic circuitry protects against single event upsets, static logic circuitry is slower than dynamic logic circuitry and thus overall performance of the integrated circuit is adversely affected. With dynamic logic circuitry, a precharge node is charged or “precharged” to a voltage corresponding to a certain logic state (e.g., high) during a precharge cycle. After the precharge cycle an input signal is evaluated and results either in the node remaining at its precharged logic state or being driven to the complementary logic state (e.g., low). A transition period corresponds to the time between when the node is precharged and when the input signal is evaluated, and during this time the node may not be driven by any component but instead is “floating.” As a result, the node is susceptible to a single event upset during this time, and such a single event upset may result in erroneous evaluation of the input signal during the subsequent evaluation period.
Various approaches have been utilized to protect against single event upsets in dynamic logic circuitry. One approach utilizes a keeper circuit that utilizes a pull-up transistor to maintain the precharge node at a desired logic level during the transition period. With this approach, the keeper circuit includes an inverter coupled between the precharge node an output node, with a pull-up PMOS transistor being coupled between a supply voltage source and the precharge node and a gate of the transistor being coupled to the output node. When the precharge node is precharged high, the inverter drives the output node low to thereby turn ON the PMOS transistor and maintain the precharge node high even after the node is done being precharged. Such a keeper circuit is not immune against single event upsets, however, since a single event upset on either the precharge node or the output node of the inverter can cause the circuit to change states. For example, assume the node is precharge high with the inverter output low and the PMOS transistor turned ON to maintain the node high. A single event upset on the precharge node, for example, may drive the precharge node sufficiently low to cause the inverter to drive its output high. When the output of the inverter goes high, the PMOS transistor turns OFF so that the precharge node remains low. The circuit has at this point erroneously changed state in response to the single event upset.
Another approach utilizes dual data paths, each including a precharge node coupled to a data keeper circuit. Dual inputs are applied, one to each data path, and each input drives the corresponding precharge node to a particular logic state. In response to a signal level on each precharge node, an output from each data path is fed back an applied to the precharge node to maintain the node at the proper logic state (i.e., either high or low). Each output is generated responsive to the logic state on the corresponding precharge node. Moreover, in one approach if the logic states on the precharge nodes differ then the data keeper circuit maintains each output at its current state, thereby inhibiting the signal on each precharge node from propagating to the outputs. In this way the data keeper circuit generates the outputs only when valid data is applied to both inputs. The dual data paths in this type of circuit drive the precharge nodes either high or low to ensure these nodes are maintained at a desired voltage level. Circuitry coupled to the precharge nodes to ensure the nodes are maintained either high or low increases the capacitance of these nodes and thereby increases the overall power consumption of the circuit since more charge must be supplied to drive the nodes to the desired voltage level. The dual data paths do, however, prevent a single event upset on any node in the circuit from erroneously changing the state of the circuit, as will be appreciated by those skilled in the art. While conventional data keeper circuits prevent single event upsets, these circuits require additional components and thus increase the overall size and power consumption of the circuitry being formed in the integrated circuit.
There is a need for a circuit and method of preventing single event upsets in dynamic logic circuitry while reducing the size and power consumption of the circuitry.